122 N 2nd St
Phoenix, AZ 85004
Riding the Wave of System-in-Package (SiP)
In the 21st century, the electronic market will be driven by consumers with demands of immediate entertainment, fast access of information, and communications anywhere in a personalized fashion and at affordable prices. The new challenge is not how many transistors can be built on a single chip as in SoC (System-on-Chip), but rather how to integrate diverse circuits together predictably, harmoniously and cost effectively. Instead of getting twice the transistors for the same cost as Moore’s Law predicted in the past 50 years, the goal of SIP is to obtain the same number of transistors for half the cost within less than half the time to market. What are the challenges that growing SiP technology bring to the failure analysis from sample preparation, fault isolation, to physical defect localization and root cause identification?
Share your experiences and advance the industry and your career at the 47th International Symposium for Testing and Failure Analysis, the premier event for the microelectronics failure analysis community. We invite you to submit your work for publication and to present to the industry in Phoenix, Arizona for the 47th year of ISTFA.